1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and in particular to generating individually accurate multiphase clocks with 50% duty cycle using a delay-locked loop (DLL).
2. Description of Related Art
To provide the functionalities required by many applications, integrated circuits (ICs) must run at ever increasing speeds. These speeds in turn require many components in an IC to be carefully timed such that they can be turned on or off precisely at different (or same) instants of time. Exemplary components could include, for example, a microprocessor for a computer, memory devices (e.g. dynamic random access memory, DRAM), and a receiver for a wireless communication device. To provide this essential timing, a delay-locked loop (DLL) can be used to generate a plurality of internal clocks that are substantially synchronized with an external clock. The better the quality of those internal clocks, i.e. the better they are synchronized, the higher the performance of the system.
FIG. 1 illustrates a conventional DLL 100 that can receive an external clock CLK and generate a plurality of internal clocks that are substantially synchronized with external clock CLK. In this embodiment, DLL 100 includes eight serially-connected delay cells 110(1)-110(8), wherein each delay cell includes a delay circuit 101 and a corresponding delay adjustment circuit 104. For example, delay cell 110(1) includes delay circuit 101(1) and delay adjustment circuit 104(1). The other delay cells in DLL 100, i.e. delay cells 110(2)-110(8), can be formed using similar components. By providing the appropriate delays to the external clock CLK, delay cells 110(1)-110(8) can generate clocks CK1-CK8, respectively, each clock having a particular phase.
For example, FIG. 2 illustrates a timing chart 200 that could be associated with DLL 100, assuming that DLL 100 could generate perfect multiphase clocks. In this embodiment, clock CK1 has a rising edge (“1”) at the end of time t1 and a falling edge (“1′”) at the end of time t5. Clock CK2 is slightly delayed because of the propagation time of CK1 through delay circuit 101(2). Therefore, clock CK2 has a rising edge (“2”) at the end of time t2 and a falling edge (“2′”) at the end of time t6. Clocks CK3-CK8 can be generated in a similar manner using delay circuits 101(3)-101(8), respectively. Because delay circuits 101(1)-101(8) are assumed to be identical, clocks CK1-CK8 have equally spacing and identical amplitude.
FIG. 3 illustrates an exemplary phase distribution chart 300 that corresponds with timing chart 200. In phase distribution chart 300, the rising and falling edges of each clock can be generically expressed as vectors N and N′, respectively, which can then be depicted in a circle having 360° (which essentially represents one time period Tperiod). Thus, in the case of 8 clocks, each clock would optimally be 45° from an adjacent clock. Notably, N and N′ are ideally in opposite direction and of equal magnitude. Thus, for example, the rising and falling edges of CK8 (i.e. “8” and “8′”, respectively) are in opposite direction and of equal magnitude. Hence, the summation of any vector N and N′ is zero.
Referring to both timing chart 200 and phase distribution chart 300, a rising edge of clock CK1 (“1”) occurs simultaneously with the falling edge of clock CK5 (“5′”). Similarly, a falling edge of clock CK1 (“1′”) occurs simultaneously with the rising edge of clock CK5 (“5”). Thus, because one signal is rising at the same time the other signal is falling, clocks CK1 and CK5 are said to be 180° out of phase with respect to each other.
When DLL 200 is in an ideal locking condition, the generated clocks, e.g. CK1-CK8, are distributed uniformly in one period of a clock cycle (Tperiod). Thus, the fundamental constraint on DLL 200 is that the total delay contributed from each delay circuit 101(1)-101(8) has to be equal to Tperiod (t1+t2+t3+. . +t8=Tperiod). The control signal used for achieving this locking condition, i.e. Vcontrol, is generated by a phase detector 102, a charge pump 103, and a loop filter (e.g. capacitor) 105, and is provided to delay cells 110(1)-110(8) via a feedback loop 106.
Specifically, phase detector 102 can compare the phase of external clock CLK on line 107 to the output of delay cell 110(8), i.e. clock CK8. If the phase of clock CK8 is slightly ahead or behind the phase of external clock CLK, then phase detector 102 can generate an appropriate signal to charge pump 103. Charge pump 103, in turn, can generate an appropriate control voltage Vcontrol, which is then provided to delay adjustment circuits 104(1)-104(8) via feedback loop 106. Capacitor 105 determines the time constant of how fast the correction can be made in DLL 100 (i.e. its bandwidth). Specifically, capacitor 105 determines the rate that the control voltage Vcontrol can be updated, wherein the smaller the capacitor the higher the bandwidth and the faster the error correction. In one embodiment, delay adjustment circuits 104(1)-104(8) can include voltage controlled current sources.
The optimal adjustment of delay adjustment circuits 104(1)-104(8) results in external clock CLK and clock CK8 having the same phase. Note that other clocks, i.e. CK1-CK7, could still exhibit some duty cycle offset, which can undesirably result in slightly indeterminate phases if delay circuits 101(1)-101(8) are not identical due to the silicon manufacturing process. Referring back to FIG. 2, clocks CK1-CK8 are each shown as having a duty cycle of 50%. That is, each clock is “on” for the same time that the clock is “off”. For example, CK3 is on during times t4-t7 and off during times t8-t11.
Notably, there are no constraints on the duty cycle of individual clocks in a conventional DLL. Unfortunately, if a duty cycle offset exists in one delay cell, it can induce mismatch and duty offset to other phases of subsequent clocks. FIG. 4 illustrates a phase distribution chart 400 including the rising and falling edges of clocks CL1-CK8 with one duty cycle offset that induces other duty cycle offsets.
Specifically, phase distribution chart 400 includes a duty cycle offset in falling clock edge 3′. Thus, the summation of vectors 3 and 3′ creates an offset vector 3off, which includes offset vector components 3off_x and 3off_y. These offset vector components adversely affect the nearest, subsequent vectors. Namely, vector component 3off_x is added to vector 4 whereas offset vector component 3off_y is added to vector 6. The resulting vectors 4 and 6 (shown by dashed lines) now also have duty cycle offsets, which were induced by offset vector 3off. These duty cycle offsets will in turn propagate to other clock phases (and so on) until an equilibrium condition is reached by feedback loop 106 of DLL 100. Thus, the uniformity of clock phases and the duty cycle of clocks from DLL 100 cannot be guaranteed.
Duty cycle correcting techniques are currently implemented after the multiphase clocks have been generated. For example, U.S. Pat. No. 6,897,693 (Kim) teaches one such technique. However, in Kim, the relationship between multiphase clocks generated by a DLL cannot be maintained. Specifically, because of the possible delay mismatch between duty correctors, the phase relationships between the generated clocks cannot be guaranteed. Kim also teaches applying duty cycle correction to an input amplifier that receives the external clock (i.e. before the DLL). However, this technique cannot ensure the duty cycles of the multiphase clocks because duty cycle offsets occur within the DLL.
Notably, in many new applications, the technology trend of higher frequency and faster data processing rate result in using both rising and falling edges of clock. Furthermore, many systems now operate with multiple clock phases. These factors impose strict requirements on the duty cycle of clocks. A DLL operating with 50% duty clocks supports a wider timing margin and hence better system performance.
Therefore, a need arises for a DLL that can provide both an accurate relationship between multiphase clocks and a duty cycle of 50% for each clock.